Stepped field plates with proximity to conduction channel and related fabrication methods

ABSTRACT

A transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent the gate and a second portion adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion of the gate. Related devices and fabrication methods are also discussed.

FIELD

The present invention relates to semiconductor devices, and moreparticularly, to transistors including field plates and relatedfabrication methods.

BACKGROUND

Materials such as silicon (Si) and gallium arsenide (GaAs) have foundwide application in semiconductor devices for low power and, in the caseof Si, low frequency applications. However, these materials may not bewell-suited for high power and/or high frequency applications, forexample, due to their relatively small bandgaps (1.12 eV for Si and 1.42for GaAs at room temperature) and relatively small breakdown voltages.

For high power, high temperature and/or high frequency applications anddevices, wide bandgap semiconductor materials may be used, such assilicon carbide (SiC) (e.g., with a bandgap of about 2.996 eV for alphaSiC at room temperature) and the Group III nitrides (e.g., with abandgap of about 3.36 eV for gallium nitride (GaN) at room temperature).These materials, typically, may have higher electric field breakdownstrengths and higher electron saturation velocities as compared to GaAsand Si.

A device of particular interest for high power and/or high frequencyapplications is the High Electron Mobility Transistor (HEMT), which isalso known as a modulation doped field effect transistor (MODFET). In aHEMT device, a two-dimensional electron gas (2DEG) may be formed at theheterojunction of two semiconductor materials with different bandgapenergies. The smaller bandgap material may have a higher electronaffinity than the wider bandgap material. The 2DEG is an accumulationlayer in the undoped smaller bandgap material and can contain arelatively high sheet electron concentration, for example, in excess of10¹³ carriers/cm². Additionally, electrons that originate in the widerbandgap semiconductor may transfer to the 2DEG, allowing a relativelyhigh electron mobility due to reduced ionized impurity scattering. Thiscombination of relatively high carrier concentration and carriermobility can give the HEMT a relatively large transconductance and mayprovide performance advantages over metal-semiconductor field effecttransistors (MESFETS) for high-frequency applications.

HEMTs fabricated in the gallium nitride/aluminum gallium nitride(GaN/AlGaN) material system can generate large amounts of radiofrequency (RF) power due to a combination of material characteristics,such as relatively high breakdown fields, relatively wide bandgaps,relatively large conduction band offset, and/or relatively highsaturated electron drift velocity. Different types of HEMTs in theGaN/AlGaN system have been demonstrated. For example, U.S. Pat. Nos.5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methodsof manufacture. In addition, U.S. Pat. No. 6,316,793, to Sheppard et al.describes a HEMT device having a semi-insulating silicon carbidesubstrate, an AlN buffer layer on the substrate, an insulating GaN layeron the buffer layer, an AlGaN barrier layer on the GaN layer, and apassivation layer on the AlGaN active structure. Moreover, U.S. Pat. No.7,045,404 to Sheppard et al. describes a HEMT device including aprotective layer and/or a low damage recess fabrication technique whichmay reduce damage to the semiconductor in the gate region of thetransistor that can occur during an anneal of the ohmic contacts of thedevice.

Electron trapping and resulting differences between DC and RFcharacteristics can be a limiting factor in the performance of thesedevices. Silicon nitride (SiN) passivation has been employed toalleviate this trapping problem resulting in high performance deviceswith power densities over 10 W/mm at 10 GHz. For example, U.S. Pat. No.6,586,781 to Wu et al. describes methods and structures for reducingtrapping effect in GaN-based transistors. However, due to the highelectric fields existing in these structures, charge trapping can stillbe a concern.

Field plates have been used to enhance the performance of GaN-basedHEMTs at microwave frequencies and have exhibited performanceimprovement over non-field-plated devices. Some field plate approachesmay involve connecting the field plate to the gate of the transistor,with the field plate on top of the drain side of a channel. Thisconfiguration can result in a reduction of the electric field on thegate-to-drain side of the transistor, thereby increasing breakdownvoltage and reducing the high-field trapping effect. However,transistors with gate-to-drain field plates can exhibit relatively poorreliability performance, particularly at class C (or higher class)operation where the electric field on the source side of the gatebecomes significant.

SUMMARY

According to some embodiments, a transistor includes a semiconductorlayer structure, a source electrode and a drain electrode on thesemiconductor layer structure, a gate on a surface of the semiconductorlayer structure between the source electrode and the drain electrode,and a field plate. The field plate includes a first portion adjacent thegate and a second portion adjacent the source or drain electrode. Thesecond portion of the field plate is farther from the surface of thesemiconductor layer structure than the first portion of the field plate,and is closer to the surface of the semiconductor layer structure thanan extended portion of the gate, which is adjacent the surface of thesemiconductor layer structure.

In some embodiments, the second portion of the field plate may beadjacent the drain electrode.

In some embodiments, the transistor may further include a spacerinsulator layer including a plurality of spacer layers that are stackedon the surface of the semiconductor layer to define first, second, andthird thicknesses that separate the first portion of the field plate,the second portion of the field plate, and the extended portion of thegate from the surface of the semiconductor layer structure,respectively.

In some embodiments, the third thickness defined by the plurality ofspacer layers may be substantially uniform at opposing sides of thegate. In some embodiments, the plurality of spacer layers may definesubstantially coplanar surfaces at opposing sides of the gate, and theextended portion of the gate may laterally extend along one of thesubstantially coplanar surfaces toward the first portion of the fieldplate.

In some embodiments, the plurality of spacer layers may include a firstspacer layer having a recess in a surface thereof, a second spacer layerincluding a first portion in the recess and a second portion on thesurface of the first spacer layer outside the recess, and a third spacerlayer having the substantially coplanar surfaces on the second spacerlayer with the field plate therebetween. The first and second portionsof the second spacer layer may be between the first and second portionsof the field plate and the surface of the semiconductor layer structure,respectively.

In some embodiments, respective upper surfaces of the first portion ofthe field plate and the second portion of the second spacer layer may besubstantially coplanar.

In some embodiments, the first and second portions of the field platemay be confined below the substantially coplanar surfaces of the thirdspacer layer.

In some embodiments, the extended portion of the gate may includesidelobe portions that laterally extend directly along the substantiallycoplanar surfaces at the opposing sides of the gate. In someembodiments, the opposing sidelobe portions of the gate may besubstantially symmetrical.

In some embodiments, sidewall spacers may separate the gate from one ormore of the plurality of spacer layers at the opposing sides thereof.The first portion of the field plate may laterally extend toward thegate and may be separated therefrom by one of the sidewall spacers.

In some embodiments, the field plate may be a first field plate, and asecond field plate may be provided on a surface of the spacer insulatorlayer and extending through a portion thereof to contact the first fieldplate. In some embodiments, the second field plate may laterally extendtoward the drain electrode beyond the second portion of the first fieldplate.

In some embodiments, the first portion of the field plate and theextended portion of the gate may laterally extend towards one anotherand may be non-overlapping in a direction perpendicular to the surfaceof the semiconductor layer structure.

In some embodiments, the semiconductor layer structure may include abuffer layer and a barrier layer that are stacked and configured todefine a two dimensional electron gas (2DEG) channel layer at aheterojunction therebetween.

According to some embodiments, a transistor includes a semiconductorlayer structure, a source electrode and a drain electrode on thesemiconductor layer structure, a gate on a surface of the semiconductorlayer structure between the source electrode and the drain electrode,and a field plate between the gate and the source or drain electrode.The field plate is closer to the surface of the semiconductor layerstructure than a laterally extended portion of the gate, and thelaterally extended portion of the gate is free of overlap with the fieldplate.

In some embodiments, the field plate may include a first portionadjacent the gate and a second portion adjacent the source or drainelectrode. The second portion may be farther from the surface of thesemiconductor layer structure than the first portion.

In some embodiments, a spacer insulator layer may include a plurality ofspacer layers that are stacked on the surface of the semiconductor layerto define first, second, and third thicknesses that separate the firstportion of the field plate, the second portion of the field plate, andthe laterally extended portion of the gate from the surface of thesemiconductor layer structure, respectively.

In some embodiments, the plurality of spacer layers may definesubstantially coplanar surfaces at opposing sides of the gate, and thelaterally extended portion of the gate may include sidelobe portionsthat laterally extend directly along the substantially coplanar surfacesat the opposing sides of the gate.

In some embodiments, the plurality of spacer layers may include a firstspacer layer having a recess in a surface thereof, a second spacer layerincluding a first portion in the recess and a second portion on thesurface of the first spacer layer outside the recess, and a third spacerlayer having the substantially coplanar surfaces on the second spacerlayer with the field plate therebetween. The first and second portionsof the second spacer layer may be between the first and second portionsof the field plate and the surface of the semiconductor layer structure,respectively.

In some embodiments, the field plate may be a first field plate, and asecond field plate may be provided on a surface of the spacer insulatorlayer and extending through a portion thereof to contact the first fieldplate. In some embodiments, the second field plate may laterally extendtoward the drain electrode beyond the second portion of the first fieldplate.

According to some embodiments, a transistor includes a channel layer anda barrier layer defining a heterojunction therebetween, a sourceelectrode and a drain electrode on the barrier layer, a gate on thebarrier layer and including sidelobe portions laterally extending fromopposing sides of the gate toward the source electrode and the drainelectrode, respectively, a field plate on the barrier layer between thegate and the drain electrode, and a spacer insulator layer including aplurality of spacer layers with the field plate therebetween. The spacerlayers are stacked on the barrier layer at the opposing sides of thegate and separate the sidelobe portions of the gate from the barrierlayer.

In some embodiments, the plurality of spacer layers may definesubstantially coplanar surfaces at the opposing sides of the gate withthe sidelobe portions of the gate laterally extending directly thereon.

In some embodiments, the spacer layers may have a substantially uniformthickness at the opposing sides of the gate.

In some embodiments, the field plate may include a first portionadjacent the gate and a second portion adjacent the drain electrode, andthe second portion may be farther from a surface of the barrier layerthan the first portion. In some embodiments, the second portion of thefield plate may be closer to the surface of the barrier layer than thesidelobe portions of the gate.

In some embodiments, the plurality of spacer layers may be stacked todefine first, second, and third thicknesses that separate the firstportion of the field plate, the second portion of the field plate, andthe sidelobe portions of the gate from the surface of the barrier layer,respectively.

In some embodiments, the first portion of the field plate and one of thesidelobe portions of the gate may laterally extend towards one anotherand may be non-overlapping in a direction perpendicular to the surfaceof the barrier layer.

In some embodiments, sidewall spacers may separate the gate from theplurality of spacer layers at the opposing sides thereof. The firstportion of the field plate may laterally extend toward the gate and maybe separated therefrom by one of the sidewall spacers.

According to some embodiments, a method of fabricating a transistorincludes forming a channel layer and a barrier layer defining aheterojunction therebetween, forming a source electrode, a drainelectrode, and a gate on the barrier layer, where the gate includessidelobe portions laterally extending from opposing sides of the gatetoward the source electrode and the drain electrode, respectively, andforming a spacer insulator layer and a field plate on the barrier layer.The spacer insulator layer includes a plurality of spacer layers withthe field plate therebetween. The spacer layers are stacked on thebarrier layer at the opposing sides of the gate and separate thesidelobe portions of the gate from the barrier layer.

In some embodiments, the plurality of spacer layers may be formed todefine substantially coplanar surfaces at the opposing sides of the gatewith the sidelobe portions of the gate laterally extending directlythereon.

In some embodiments, the field plate may be formed to include a firstportion adjacent the gate and a second portion adjacent the drainelectrode, and the second portion may be farther from a surface of thebarrier layer than the first portion.

In some embodiments, forming the spacer insulator layer and the fieldplate may include forming a first spacer layer comprising a recess in asurface thereof, forming a second spacer layer comprising a firstportion in the recess and a second portion on the surface of the firstspacer layer outside the recess, forming the first and second portionsof the field plate on the first and second portions of the second spacerlayer, respectively, and forming a third spacer layer on the secondspacer layer and the first and second portions of the field plate.

In some embodiments, the field plate may be a first field plate. Themethod may further include forming an opening extending through thethird spacer layer to expose at least one of the first or secondportions of the first field plate, and forming a second field plate onthe third spacer layer and extending into the opening to contact thefirst field plate.

Other devices and methods according to some embodiments will becomeapparent to one with skill in the art upon review of the followingdrawings and detailed description. It is intended that all suchadditional embodiments, in addition to any and all combinations of theabove embodiments, be included within this description, be within thescope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-section of a unit cell of a transistordevice including a buried field plate according to some embodiments ofthe present invention.

FIGS. 2-12 are schematic cross-sectional views illustrating exemplaryintermediate fabrication steps in methods for fabricating transistordevices according to some embodiments of the present invention.

FIG. 13 is a schematic cross-section of a unit cell of a transistordevice including a buried field plate according to further embodimentsof the present invention.

FIG. 14 is a schematic cross-section of a unit cell of a transistordevice including a buried field plate according to still furtherembodiments of the present invention.

FIG. 15 is a schematic cross-section of a unit cell of a transistordevice including a buried field plate according to yet furtherembodiments of the present invention.

DETAILED DESCRIPTION

Field plates are conductive structures that can be configured to alterthe electric field distribution in a channel region of transistordevices to improve operating characteristics (e.g., breakdown voltage,gain, maximum operating frequency) of the devices. For example, in HEMTsor other semiconductor-based field-effect transistor (FET) devices,large electric fields may arise during normal operation in thegate-drain region. Field plates may be configured to reduce the peakelectric field in the device active region for a given bias voltage.Such field plates may not only manage field distribution, but may alsoaffect both the drain-to-source and gate-to-drain capacitances C_(ds),C_(gd). Field plates positioned between the gate and drain (alsoreferred to as the gate-drain region) may also be configured to modulatethe device active region, resulting in a decrease of surface trappingeffects that can affect proper device operation under large radiofrequency (RF) signals. More generally, field plates may function toalleviate detrimental effects (low breakdown voltage, charge trappingphenomena, poor reliability) that may arise when a device is operated ata high electric field.

Embodiments of the present invention provide particular configurationsand fabrication methods for field plate structures that can reducecapacitance, trapping effects, and/or peak electric field distribution.In particular, embodiments of the present invention allow forfabrication of stepped or graded field plate structures, whereby thespacing or separation between the conduction channel and the field plateis reduced. In some embodiments, the field plate may be provided betweenthe gate and the drain, to thereby reduce gate-to-drain capacitanceC_(gd) and peak electric field in proximity to the drain supply voltage.

For example, a buried field plate may include a first portion adjacentthe gate that is separated from a surface of a semiconductor layerstructure (in which a conduction channel is induced or otherwisedefined) by a first distance or spacing, and a second portion adjacentthe drain electrode that is separated from the surface of thesemiconductor layer by a second distance or spacing that is greater thanthe first distance or spacing. A recess in in a spacer layer adjacentthe gate may be used to define the first and second portions of theburied field plate in a stepped geometry (with the first and second stepportions at the different distances or spacings from the semiconductorlayer surface) and/or a graded geometry (with a graded portion extendingfrom one of or connecting the step portions). In some embodiments, anadditional sidewall spacer may be included to control a lateral spacingbetween the gate and the field plate. As used herein, the term “lateral”refers to a direction that is substantially parallel with respect to amajor surface of the semiconductor layer structure. Also, someembodiments may include a second or additional field plate that extendsthrough one or more spacer layers to contact the buried field plate,thereby defining a second “step” in the stepped or graded field platestructure. Providing the buried field plate in closer proximity to thegate and/or the conduction channel may enhance or improve reduction inC_(gd) and trapping effects. The stepped or graded field plate structuremay also reduce the peak electric field in proximity to the drain supplyvoltage.

FIG. 1 is a schematic cross-section of a unit cell of a transistorstructure including a buried field plate according to some embodimentsof the present invention. In particular, FIG. 1 illustrates an exampleof a HEMT including a buried field plate having a stepped or gradedstructure as described herein.

A HEMT includes a channel layer and a barrier layer on the channellayer. Source and drain electrodes may be formed as ohmic contacts withthe barrier layer. A gate is formed on a surface of the barrier layerbetween the source and drain electrodes, and a spacer insulator layer isformed above the barrier layer. Depending on configuration, the spacerinsulator layer may be formed before or after formation of the gate. Thespacer insulator layer may be a dielectric layer, a layer of undoped ordepleted Al_(x)Ga_(1-x)N (0≤x≤1) material, or a combination thereof. Aconductive field plate is formed in the spacer insulator layer andextends a distance Lf from the gate towards the source or drainelectrode. The field plate may be electrically connected to the sourceelectrode. The electrical connection between the field plate and thesource electrode may be outside the active region of the device in somecases. The field plate may reduce the peak electric field in the deviceresulting in increased breakdown voltage and reduced charge trapping.The reduction of the electric field may also yield other benefits suchas reduced leakage currents and enhanced reliability.

The HEMT may include a Group-III nitride based semiconductor layerstructure, although other material systems can also be used. It shouldbe noted that while described herein primarily with reference tofabrication of a HEMT, the elements and concepts of embodimentsdescribed herein can be applied to many different types of transistorstructures, including but not limited to Metal Semiconductor FieldEffect Transistors (MESFETs) and Metal Oxide SemiconductorHeterostructure Field Effect Transistors (MOSHFETs).

Referring now to FIG. 1, a HEMT 100 includes GaN-based or other GroupIII nitride-based semiconductor layer structure 24 on a substrate 10.Group III nitrides may refer to semiconductor compounds formed betweennitrogen and the elements in the Group III of the periodic table, suchas aluminum (Al), gallium (Ga), and/or indium (In) to form binary (e.g.,GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN)compounds. Accordingly, formulas such as Al_(x)Ga_(1-x)N, where 0≤x≤1,may be used to describe these compounds. The substrate 10 may includesilicon carbide, silicon, sapphire, spinel, zinc oxide, silicon, galliumarsenide, zinc oxide, or any other material capable of supporting growthof Group III-nitride materials. Silicon carbide may have a closercrystal lattice match to Group III than sapphire, and may allow forformation of higher-quality Group III nitride films thereon. Siliconcarbide also has a very high thermal conductivity, such that the totaloutput power of Group III nitride devices on silicon carbide may not belimited by the thermal dissipation of the substrate (as may be the casewith some devices formed on sapphire).

Optional buffer, nucleation and/or transition layers may also be formedon the substrate 10. For example, a nucleation layer 15 can be formed onthe substrate 10 to reduce the lattice mismatch between the substrate 10and the next layer of the semiconductor layer structure 24. Theformation and composition of the nucleation layer 15 can depend on thematerial used for the substrate 10. For example, An Al_(z)Ga_(1-z)N(0≤z≤1) nucleation layer 15 can be grown on the substrate 10 viaepitaxial growth methods, such as MOCVD (Metalorganic Chemical VaporDeposition), HVPE (Hydride Vapor Phase Epitaxy) or MBE (Molecular BeamEpitaxy). Methods of forming a nucleation layer 15 on various substratesare described in U.S. Pat. No. 5,290,393 to Nakamura and U.S. Pat. No.5,686,738 to Moustakas. Methods of forming nucleation layers on siliconcarbide substrates are described in U.S. Pat. No. 5,393,993 to Edmond etal., U.S. Pat. No. 5,523,589 to Edmond et al., and U.S. Pat. No.5,739,554 to Edmond et al.

The semiconductor layer structure 24 of the HEMT 100 includes a channellayer 20 and a barrier layer 22. The channel layer 20 may be formed onthe nucleation layer 15. A barrier layer 22 may be formed on the channellayer 20 opposite the nucleation layer 15 and the substrate 10. One orboth of the channel layer 20 and the barrier layer 22 may includesub-layers including doped or undoped (i.e., “unintentionally doped”)layers of Group III-nitride materials, including material compositionswhich may be stepwise or continuously graded. In some embodiments, thechannel layer 20 may include one or more layers ofAl_(x)Ga_(y)In_((1-x-y))N where 0≤x≤1, 0≤y≤1, and x+y≤1. For example,the channel layer 20 may be a GaN layer. In some embodiments, thebarrier layer 22 may include one or more layers of Al_(x)Ga_(1-x)N orAl_(x)In_(y)Ga_(1-x-y)N, where 0≤x≤1, 0≤y≤1, and x+y≤1. Thesemiconductor layer structure 24 may be an epitaxial structure includingthese and/or other layers formed on the substrate 10 via epitaxialgrowth methods. For example, the channel and barrier layers 20, 22 canbe formed using the same or similar methods used to grow the nucleationlayer 15. Electrical isolation between devices can be accomplishedthrough mesa etch or ion implementation outside the active region of theHEMT 100.

In the HEMT device 100, the channel layer 20 and the barrier layer 22may be formed of materials having different bandgaps, such that aheterojunction is defined at an interface between the channel layer 20and the barrier layer 22. In particular, where both the channel layer 20and the barrier layer 22 are formed of Group III-nitride layers, thechannel layer 20 may be a GaN layer, and the barrier layer 22 may be anAlGaN layer. A 2DEG conduction channel 40 can be induced at theheterointerface between the channel layer 20 and the barrier layer 22,and the channel layer 20, 2DEG conduction channel 40 and barrier layer22 can generally form the active region of the HEMT 100.

In other embodiments, the channel layer 20 and the barrier layer 22 mayhave different lattice constants. For example, the barrier layer 22 maybe a relatively thin layer having a smaller lattice constant than thechannel layer 20, such that the barrier layer 22 “stretches” at theinterface between the two. Accordingly, a pseudomorphic HEMT (pHEMT)device may be provided. Example HEMT structures are illustrated in U.S.Pat. No. 6,316,793 to Sheppard et al., U.S. Pat. No. 6,586,781 to Wu etal., U.S. Pat. No. 6,548,333 to Smith and U.S. Patent ApplicationPublication Nos. 2002/0167023 to Prashant et al., and 2003/0020092 toParikh et al. Other nitride based HEMT structures are illustrated inU.S. Pat. No. 5,192,987 to Kahn et al. and U.S. Pat. No. 5,296,395 toKahn et al.

Source and drain electrodes 30 are formed on the semiconductor layerstructure 24 to define ohmic contacts with the barrier layer 22. A gate32 is formed on a surface of the barrier layer 22 between the source anddrain electrodes 30. Electrical current can flow between the source anddrain electrodes 30 through the 2DEG conduction channel 40 at theheterointerface defined by the channel layer 20 and the barrier layer 22when the gate 32 is biased at the appropriate level.

Formation of the gate 32 may include depositing a dielectric or otherspacer insulator layer 25, etching through the spacer insulator layer 25using a mask and/or other sacrificial layer, and depositing a gate intothe etched portion of the spacer insulator layer 25. Formation of sourceand drain electrodes 30 may be likewise performed, as described by wayof example in the patents and publications referenced above. In someembodiments, the gate 32 may include one or more extended portions thatlaterally extend onto portions of the spacer insulator layer 25, forexample, opposing sidelobe portions 32 a, 32 b that define a T-shape(also referred to herein as a “T-gate”). The gate 32 and sidelobeportions 32 a, 32 b can define multiple different lengths (L_(G1) andL_(G2)). The sidelobe portions 32 a, 32 b may extend substantiallysymmetrically onto the spacer insulator layer 25 at opposing sides ofthe gate 32 in some embodiments.

As shown in FIG. 1, the spacer insulator layer 25 includes multiplespacer layers 26, 27, 28 that are sequentially stacked on the surface 24s of the semiconductor layer structure 24. The spacer insulator layer 25also includes a buried field plate 33 between the spacer layers 26, 27,28 at one side of the gate 32. The buried field plate 33 includes metalor other conductive materials, for example, copper, gold, and/or acomposite metal. In some embodiments, the buried field plate 33 may bepositioned between the gate 32 and a drain electrode 30 so as to reducethe peak or otherwise redistribute the electric field, to reducegate-to-drain capacitance C_(gd), and/or to reduce trapping effects onthe drain side of the HEMT 100. A buried field plate having a similarstepped structure (not shown) may additionally or alternatively bepositioned between the gate 32 and the source electrode 30 in someembodiments.

The buried field plate 33 has a stair-step profile including two or moreportions, illustrated by way of example herein with reference to a firststep portion 33 a adjacent the gate 32 and a second step portion 33 badjacent the drain electrode 30. The step portions 33 a, 33 b of thefield plate 33 may be defined by a continuous layer, or by a stack ofdiscontinuous layers. That is, the step portions 33 a, 33 b of the fieldplate 33 may be defined by a single layer or by multiple layers. In someembodiments, the step portions 33 a, 33 b may include a discontinuitytherebetween. Each step portion 33 a, 33 b of the field plate 33 ispositioned at a different distance or spacing from the surface 24 s (andthus, the underlying conduction channel 40). The field plate 33including first and second step portions 33 a and 33 b at closer andfarther distances or spacings from the conduction channel 40 may allowfor reduction of C_(gd) and trapping effects, as well as reduction inpeak electric field proximate the drain electrode 30.

In particular, as shown in FIG. 1, the spacer layers 26, 27 may besequentially stacked to define different thicknesses between the firstand second portions 33 a, 33 b of the buried field plate 33 and thesurface 24 s to provide the different spacings S1, S2. For example, thespacer layer 26 may include a recess therein such that when the spacerlayer 27 and the buried field plate 33 are sequentially formed on thespacer layer 26 and in the recess, the portion 33 a of the field plate33 is closer to the surface 24 s than the portion 33 b.

In addition, the spacer layers 26, 27, 28 may separate the sidelobeportions 32 a, 32 b from the surface 24 s at opposing sides of the gate32. For example, the spacer layers 26, 27, 28 may define a substantiallyuniform thickness or spacing S3 and/or coplanar surfaces at oppositesides of the gate 32, onto which the sidelobe portions 32 a, 32 b of thegate 32 extend. In some embodiments, the sidelobe portion 32 a of thegate 32 and the step portion 33 a of the field plate 33 may beoverlapping and separated by portions of the third spacer layer 28. Insome embodiments, the sidelobe portion 32 a of the gate 32 and the stepportion 33 a of the field plate 33 may be non-overlapping in a directionperpendicular to the surface 24 s.

The spacer layers 26, 27, 28 may be formed to position the second stepportion 33 b of the buried field plate 33 farther from the surface 24 sof the semiconductor layer structure 24 (and thus, the conductionchannel 40) than the first step portion 33 a, and closer to the surface24 s of the semiconductor layer structure 24 than the sidelobe portions32 a, 32 b of the gate 32. More generally, the spacer insulator layer 25may be a multi-layer stack with layers 26, 27, 28 having respectivethicknesses that can be formed to control the distance or spacingbetween the gate sidelobe portions 32 a, 32 b and the surface 24 s, thedistance or spacing between the field plate step portions 33 a, 33 b andthe surface 24 s, and/or the distance or spacing between the gatesidelobe portions 32 a, 32 b and the field plate step portions 33 a, 33b.

The HEMT 100 may also include an additional or second field plate 34that extends through an upper spacer layer 29 to contact the firstand/or second step portions 33 a, 33 b of the buried field plate 33. Thesecond field plate 34 may also have a stepped or graded structure, witha first portion 34 a that is closer to the surface 24 s of thesemiconductor layer structure 24 than a second portion 34 b. The firstportion 34 a of the second field plate 34 may also be closer to thedrain electrode 30, and may allow for further control of C_(gd),trapping effects, and/or peak electric field proximate the drainelectrode 30.

Although illustrated in FIG. 1 in a planar HEMT configuration with thegate 32 and the source and drain electrodes 30 on the surface 24 s ofthe barrier layer 22, it will be understood that buried field plates 33with stepped or graded field structures in accordance with embodimentsof the present invention may be used in other HEMT configurations, suchas recessed gate HEMTs (where the source and drain electrodes 30 areelevated relative to the gate 32 on the surface 24 s) and recessedsource/drain HEMTs (where the source and drain electrodes 30 extendtoward the channel layer 20 beyond the surface 24 s).

FIGS. 2-12 are schematic cross-sectional views illustrating exemplaryintermediate fabrication steps in methods for fabricating transistordevices according to some embodiments of the present invention. Theexamples of FIGS. 2-12 illustrate fabrication of a buried field platehaving a stepped or graded structure between the gate and drainelectrode of the transistor device; however, it will be understood thatsimilar fabrication steps may be additionally or alternatively used tofabricate a field plate (not shown) between the gate and the sourceelectrode in some embodiments.

As shown in FIG. 2, a first spacer layer 26 is formed on a surface 24 sof a semiconductor layer structure 24 including a barrier layer 22 thatdefines a heterojunction with an underlying channel layer 20. Asdiscussed above, the channel layer 20 and the barrier layer 22 may be anepitaxial structure (e.g., including Group III nitride materials) formedvia epitaxial growth methods. A nucleation layer 15 can be formed on thesubstrate 10 (e.g., a SiC substrate) to reduce lattice mismatch with thesubstrate 10. The first spacer layer 26 may be a dielectric or otherinsulator layer that is blanket formed on the barrier layer 22. Forexample, the first spacer layer 26 may be a silicon nitride or siliconoxide layer formed by high quality sputtering and/or vapor depositionmethods.

In FIG. 3, an aperture or recess 26 r is defined in the first spacerlayer 26. For example, the recess 26 r may be optically defined andopened using a mask that exposes a portion of the spacer layer 26. Thelateral position and/or width of the recess 26 r may be selected toprovide the step portions 33 a, 33 b of the buried field plate 33 atdesired distances from the gate and drain electrode to be formed in asubsequent step. The recess 26 r may extend through the spacer layer 26to expose the surface 24 s of the semiconductor layer structure 24 insome embodiments.

In FIG. 4, a second spacer layer 27 is formed on the first spacer layer26. The second spacer layer 27 may conformally extend along the surfaceof the first spacer layer 26 and into the recess 26 r along a bottomsurface and sidewalls of the recess 26 r to define a step differencebetween portions thereof within and outside the recess 26 r. The secondspacer layer 27 may likewise be a dielectric or other insulator layer(e.g., a silicon nitride or silicon oxide layer), and may be formed bysimilar or different methods than the first spacer layer 26.

FIG. 5 illustrates formation of a field plate 33 on the second spacerlayer 27. For example, a metal or other conductive layer may be formedon portions of the second spacer layer 27 using a masking and/orpatterning process. The step difference defined by the portions of thesecond spacer layer 27 within and outside the recess 26 r in the firstspacer layer 26 results in the field plate 33 including first and secondportions 33 a and 33 b in a stepped configuration. A graded portion mayconnect the step portions 33 a and 33 b. The thickness of the secondspacer layer 27 in the recess 26 r defines a first distance or spacingSi that separates the first portion 33 a of the buried field plate 33from the surface 24 s, while the combined thicknesses of the firstspacer layer 26 and the second spacer 27 on the surface thereof outsidethe recess 26 r defines a second distance or spacing S2 that separatesthe second portion 33 b of the buried field plate 33 from the surface 24s.

The first portion 33 a of the field plate 33 may laterally extend on thesecond spacer layer 27 by a distance L_(fs) toward one side (e.g., thesource side) of the device. The second portion 33 b of the field plate33 may laterally extend on the second spacer layer 27 by a distanceL_(fd) toward another side (e.g., the drain side) of the device. L_(fs)and L_(fd) can be the same or different distances. In some embodiments,the portions 33 a, 33 b of the field plate 33 at the different spacingsS1, S2 from the surface 24 s may not be continuous. For example, thefirst portion 33 a may be formed on the portion of the second spacerlayer 27 in the recess 26 r, and the second portion 33 b may beseparately formed on the surface of the second spacer layer 27 outsidethe recess or may otherwise include a discontinuity with the firstportion 33 a. That is, the first and second portions 33 a, 33 b of thefield plate 33 may be defined by a single continuous layer or bymultiple stacked layers.

By forming the recess 26 r in FIG. 3, forming the second spacer layer 27in the recess 26 r in FIG. 4, and forming the first portion 33 a of theburied field plate 33 in the recess 26 r in FIG. 5, the first portion 33a of the field plate 33 is closer to the surface 24 s than the secondportion 33 b of the field plate 33. The reduced thickness Si of thedielectric or other spacer insulator layer 25 between the portion 33 aof field plate 33 and the surface 24 s may reduce capacitance resultingfrom providing the field plate 33 between the gate and the drainelectrode (e.g., relative to a planar field plate having a uniformspacing S2 from the surface 24 s).

In FIG. 6, a third spacer layer 28 is formed on the second spacer layer27 and on the field plate 33. The third spacer layer 28 may conformallyextend along the surface of the second spacer layer 27 and the steppedportions 33 a, 33 b of the field plate 33 to define a buried field plateconfiguration. The third spacer layer 28 may likewise be a dielectric orother insulator layer (e.g., a silicon nitride or silicon oxide layer),and may be formed by similar or different methods than the first and/orsecond spacer layers 26 and/or 27. The first, second, and third spacerlayers 26, 27, 28 may collectively define the spacer insulator layer 25as described herein.

The spacer layers 26, 27, 28 of the spacer insulator layer 25 describedherein may be dielectric material, such as silicon nitride, aluminumnitride, silicon dioxide, and/or other suitable material. Othermaterials may also be utilized for the layers 26, 27, 28 of the spacerinsulator layer 25. For example, the spacer layers 26, 27, 28 may alsoinclude magnesium oxide, scandium oxide, aluminum oxide and/or aluminumoxynitride. The spacer layers 26, 27, 28 may have the same or differentthicknesses. In some embodiments, the first spacer layer 26 may have asmaller thickness than the second spacer layer 27, and/or the secondspacer layer 27 may have a smaller thickness than the third spacer layer28. The spacer insulator layer 25 may include a portion P having asubstantially uniform thickness or spacing S3 relative to the surface 24s of the semiconductor layer structure 24, and a portion having anon-uniform thickness or spacing S4.

As noted above, although illustrated with reference to a field plate 33including two step portions 33 a, 33 b, stepped or graded field platesin accordance with embodiments of the present invention may includeadditional step portions. For example, still referring to FIG. 6, anadditional aperture or recess (not shown) may be formed in the thirdspacer layer 28 to expose at least part of the second portion 33 b ofthe field plate, and additional step portions of the field plate 33 (notshown) may be formed on the second portion 33 b of the field plate 33exposed by the additional recess and on the surface of the third spacerlayer 28 outside the additional recess. More generally, whileillustrated with reference to fabrication of a spacer insulator layer 25including three spacer layers 26, 27, 28 and a field plate 33 includingtwo step portions 33 a, 33 b, it will be understood that spacerinsulator layers 25 with more than three spacer layers and field plates33 with more than two step portions may be fabricated in accordance withembodiments described herein.

FIG. 7 illustrates formation of an aperture or opening 25 o in theportion P of the spacer insulator layer 25, where the gate may be formedin a subsequent step. For example, the opening 25 o may be opticallydefined and opened using a mask that exposes a portion of the thirdspacer layer 28. As shown in FIG. 7, the opening 25 o extends throughthe spacer layers 28, 27, 26 to expose a portion of the surface 24 s ofthe semiconductor layer structure 24 (i.e., a surface of the barrierlayer 22). The opening 25 o may be formed utilizing a patterned mask anda low-damage etch with respect to the barrier layer 22. The opening 25 omay be offset between the source and drain such that the opening 25 o,and subsequently the gate, may be closer to the source electrode thanthe drain electrode. Also, although illustrated as being uniform inwidth, it will be understood that the opening 25 o may be wider in someportions, due to isotropy of the etch with respect to the multiplelayers 26, 27, 28 of the spacer insulator layer 25.

As shown in FIG. 8, sidewall spacers 25 s are formed at opposingsidewalls in the opening 25 o of the spacer insulator layer 25. Forexample, the sidewall spacers 25 s may be formed to define a desiredfirst gate length L_(G1) to be formed in a subsequent step, particularlyin embodiments where the gate opening 25 o is non-uniform in width asnoted above. In some embodiments, the sidewall spacers 25 s may beformed using a spacer insulator shrink process. The sidewall spacers 25s may likewise be a dielectric or other insulator layer (e.g., a siliconnitride or silicon oxide layer), and may separate the lateral extensionof the first portion 33 a of the buried field plate 33 from contactingthe gate 32.

FIG. 9 illustrates formation of the gate 32 in the opening 25 o in thespacer insulator layer 25. The gate 32 extends through the spacerinsulator layer 25 to contact the exposed portion of the barrier layer22. The gate 32 may be formed via a metallization process in the opening25 o directly on the sidewall spacers 25 s at the opposing sidewalls ofthe spacer insulator layer 25, such that gaps may not be formed betweenthe two. Suitable gate materials may depend on the composition of thebarrier layer 22. However, in certain embodiments, materials capable ofmaking a Schottky contact to a nitride based semiconductor material maybe used for the gate 32, such as Ni, Pt, NiSi_(x), Cu, Pd, Cr, TaN, Wand/or WSiN.

The gate 32 includes one or more extended portions (illustrated asopposing sidelobes portions 32 a, 32 b) that laterally extend on surfaceportions of the spacer insulator layer 25 outside the opening 25 o todefine a second gate length L_(G2). The sidelobe portions 32 a, 32 b maybe integral to the gate 32. The length by which the sidelobe portions 32a, 32 b extend onto the spacer insulator layer 25 at opposing sides ofthe gate 32 may be controlled in the fabrication process. In someembodiments, the sidelobe portion 32 a may be longer (and thus, define agreater portion of the second gate length L_(G2)) than the sidelobeportion 32 b, or vice versa. In other embodiments, the sidelobe portions32 a and 32 b may laterally extend along the surface of the third spacerlayer 28 by substantially the same length at opposing sides of the gate32. Gate-to-drain capacitance (C_(gd)) and/or gate-to-source capacitance(C_(gs)) of the transistor device, which may be due to the sandwichingof the portions of the spacer insulator layer 25 between the sidelobeportions 32 a, 32 b and the semiconductor layer structure 24, may befurther controlled as described below.

As shown in FIG. 9, the gate 32 is formed such that the sidelobeportions 32 a and 32 b are separated from the surface 24 s of thesemiconductor layer structure 24 s (and thus, the conduction channeldefined at the heterojunction between barrier layer 22 and channel layer20) by a substantially uniform distance or spacing S3 at opposite sidesof the gate 32. In embodiments described herein, the buried field plate33 having the stepped shape may be configured to increase a planarity ofthe third spacer layer 28 on which the sidelobe portions 32 a and 32 bof the gate 32 extend, such that the spacer insulator layer 25 includessubstantially coplanar surfaces at the opposing sides of the gate 32,with the first and second portions 33 a and 33 b of the field plate 33confined therebelow.

In particular, due to the recess 26 r in the first spacer layer 26formed in FIG. 3, an upper surface of the first portion 33 a of theburied field plate 33 may be substantially coplanar with the uppersurface of the second spacer layer 27 on which the third spacer layer 28is formed. As such, when the third spacer layer 28 is formed on thefield plate 33 and the second spacer layer 27 in FIG. 6, the surface ofportion P of the spacer insulator layer 25 in which the gate opening 25o is formed may be substantially planar, such that the sidelobe portions32 a and 32 b formed thereon at opposite sides of the gate 32 may beformed on substantially coplanar surfaces and uniformly spaced from thesurface 24 s of the semiconductor layer structure 24 by a spacing S3. Incontrast, portions of the third spacer layer 28 formed on the secondstep portion 33 b of the field plate 33, which is outside the recess 26r may have a non-uniform thickness (shown by spacing S4). The stepped orgraded structure of the buried field plate 33 increases a distancebetween the non-uniform thickness S4 of the third spacer layer 28 andthe portion P in which the gate 32 is formed, such that the sidelobes orwings 32 a and 32 b are spaced apart from the surface 24 s by theuniform spacing S3. In some embodiments, the gate 32 may be formed withsidelobes or wings 32 a and 32 b that extend substantially symmetricallyon opposite sides of the gate 32.

In FIG. 10, a fourth spacer layer 29 is formed on the gate 32 and thethird spacer layer 28. The fourth spacer layer 29 may conformally extendalong the sidelobes 32 a, 32 b and upper surface of the gate 32, andalong the surface of the third spacer layer 28. The fourth spacer layer29 may likewise be a dielectric or other insulator layer (e.g., asilicon nitride or silicon oxide layer), and may be formed by similar ordifferent methods than the first, second, and/or third spacer layers 26,27, 28. In some embodiments, the fourth spacer layer 29 may be apassivation layer that is formed at lower temperatures than the first,second, and/or third spacer layers 26, 27, 28, as such highertemperatures may not be feasible once the gate metallization has beendeposited.

In FIG. 11, an aperture or opening 290 is formed in the fourth spacerlayer 29 to expose a portion of the field plate 33. For example, theopening 290 may be optically defined and opened using a mask thatexposes a portion of the fourth spacer layer 29 overlying the fieldplate 33. As shown in FIG. 11, the opening 290 extends through thespacer layers 29, 28 to expose a surface of the second portion 33 b ofthe buried field plate 33. The opening 290 may additionally oralternatively expose a surface of the first portion 33 a of the buriedfield plate 33.

FIG. 12 illustrates formation of an additional or second field plate 34in the opening 290 to contact the buried field plate 33. The secondfield plate 34 is a conductive structure that extends through the spacerlayers 29, 28 to contact the first and/or second portions 33 a, 33 b ofthe buried field plate. The second field plate 34 may also have astepped or graded structure, with a first portion 34 a that is closer tothe surface 24 s of the semiconductor layer structure 24 than a secondportion 34 b. A step difference between surfaces of the first and secondportions 34 a and 34 b of the second field plate 34 may be the same asor different than a step difference between surfaces of the first andsecond portions 33 a and 33 b of the buried field plate 33. The lateralextension of the first portion 34 a of second field plate 34 toward thesource or drain (S/D) may be controlled so as to further reduce the peakor otherwise redistribute the electric field without substantiallyreducing the breakdown voltage beyond a threshold. Although notillustrated, source and drain electrodes may be formed on the barrierlayer 22 (e.g., by etching openings into the spacer insulator layer 25to expose the underlying barrier layer 22 and depositing ohmic contactsthereon) to arrive at the device 100 of FIG. 1.

FIGS. 13-15 are schematic cross-sections of unit cell of a transistorstructure including buried field plates having various stepped or gradedstructures according to further embodiments of the present invention. Inparticular, FIGS. 13-15 illustrate examples of HEMTs 100′, 100″, and100′ including a stepped or graded buried field plate structures 33′,33″, and 33′, respectively. Some elements or layers of the HEMTs 100′,100″, and 100′ may be similar to those of the HEMT 100 of FIG. 1 andrepeated description thereof is omitted.

For example, FIG. 13 illustrates a buried field plate 33′ having firstand second step portions 33 a′ and 33 b′ defined by respective layers,rather than a single continuous layer as shown in FIG. 1. The stepportions 33 a′ and 33 b′ of the field plate 33′ are positioned atdifferent distances or spacings S1 and S2, respectively, from thesurface 24 s (and thus, the underlying conduction channel 40) of thesemiconductor layer structure. Respective upper surfaces of the firstportion of the field plate 33 a′ and the second spacer layer 27 may besubstantially coplanar. In some embodiments, the step portions 33 a′ and33 b′ may include a discontinuity therebetween.

In embodiments described herein, the first portion 33 a of the buriedfield plate 33 laterally extends by the length L_(fs) toward the gate32, and the sidelobe portion 32 a of the gate 32 laterally extendstoward the buried field plate 33 by a portion of the gate length L_(G2).In the embodiments of FIGS. 1 to 13, a lateral spacing or separation ismaintained between the first portion 33 a of the buried field plate 33and the sidelobe portion 32 a of the gate 32, such that the laterallyextending sidelobe portion 32 a of the gate 32 is free of overlap withthe field plate 33. That is, the first portion 33 a of the field plate33 is confined outside an edge or boundary of the sidelobe portion 32 aand does not extend between the sidelobe portion 32 a and the surface 24s of the semiconductor layer structure 24, such that the first portion33 a of the buried field plate 33 and the sidelobe portion 32 a of thegate 32 are non-overlapping in a direction perpendicular to the surface24 s (also referred to herein as vertical overlap). However, embodimentsof the present invention are not limited to any particular length of thefirst portion 33 a of the buried field plate 33, which may overlap withthe laterally extending sidelobe portions 32 a, 32 b in someembodiments.

FIG. 14 is a schematic cross-section of a unit cell of a transistorstructure including a buried field plate 33″ where the first portion 33a″ of the buried field plate 33″ laterally extends toward the gate 32beyond an edge of the sidelobe portion 32 a. The first portion 33 a″ ofthe buried field plate 33″ vertically overlaps the sidelobe portion 32 aof the gate 32, and may further extend a distance from between an edgeof the sidelobe portion 32 a up to the sidewall spacer 25 s. As in otherembodiments described herein, electrical isolation between the firstportion 33 a″ of the field plate 33″ that overlaps with the sidelobeportion 32 a of the gate 32 is provided by portions of the spacerinsulator layer 25 therebetween, in particular, by the third spacerlayer 28. Also, one of the sidewall spacers 25 s provides electricalisolation between the lateral extension of the first portion 33 a″ ofthe buried field plate 33″ and the gate 32.

In the example of FIG. 14, the first portion 33 a″ laterally extendsalong an entirety of the portion of the surface 24 s between the gate 32and the field plate 33″ and contacts the sidewall spacer 25 s. However,the amount of overlap of the first portion 33 a″ of the buried fieldplate 33″ and the sidelobe portion 32 a of the gate 32 and the lengthL_(fs) by which the first portion 33 a″ extends on the gate-drain regioncan be varied.

FIG. 15 is a schematic cross-section of a unit cell of a transistorstructure including a buried field plate 33′″ where the first portion 33a′″ of the buried field plate 33′″ also laterally extends toward thegate 32 and beyond an edge of the sidelobe portion 32 a, but along lessthan an entirety of the portion of the surface 24 s between the gate 32and the field plate 33″. That is, the first portion 33 a′″ of the buriedfield plate 33′″ vertically overlaps the sidelobe portion 32 a of thegate 32, but does not contact the sidewall spacer 25 s. As such, thefirst portion 33 a′″ of the field plate 33 may be laterally separatedfrom a sidewall of the gate 32 by a thickness of the sidewall spacer 25s or more. In FIG. 15, the first and second step portions 33 a′″ and 33b′″ are defined by respective layers, rather than a single continuouslayer. The first and second step portions 33 a′″ and 33 b′″ mayvertically overlap. Respective upper surfaces of the first portion 33a′″ of the field plate 33′″ and the second spacer layer 27 may besubstantially coplanar. The first portion 33 a′″ of the field plate 33′″extends between one of the substantially coplanar surfaces of the thirdspacer layer 28 and the surface 24 s. Electrical isolation between thefirst portion 33 a′″ of the field plate 33′″ overlapping with thesidelobe portion 32 a of the gate 32 is provided by portions of thethird spacer layer 28 therebetween.

According to embodiments of the present invention, by forming the spacerinsulator layer 25 with varying thicknesses Si, S2, and S3 that separatefield plate step portions 33 a, 33 b, and gate sidelobe portion 32 afrom the surface 24 s of the semiconductor layer structure 24, acapacitance between the gate 32 and the source or drain electrodes 30may be reduced (e.g., relative to a planar field plate separated fromthe surface 24 s by a spacer insulator layer having a uniformthickness). Capacitance can further be reduced and/or adjusted byavoiding and/or controlling vertical overlap between the field plateportion 33 a and the gate sidelobe portion 32 a in accordance withembodiments described herein.

In some embodiments, the stepped construction of the buried field platemay contribute to the reduction in peak electric field proximate to thedrain. In particular, by forming the buried field plate 33 with thestepped structure 33 a, 33 b by forming the spacer insulating layer 25with a greater thickness S2 between the second portion 33 b of theburied field plate 33 and the surface 24 s of the semiconductor layerstructure 24 (and thus, closer to the conduction channel 40 defined atthe heterojunction between barrier layer 22 and channel layer 20), apeak electric field adjacent the drain may be reduced, which may alsoreduce charge trapping effects.

Embodiments of the present invention are thus generally directed totransistor structures where a buried field plate is separated from thebarrier layer by a differing distances or spacings. In some embodiments,the field plate can be separated from the semiconductor layer structuresby one or more thinner spacer layers, while one or more thicker spacerlayers can separate the field plate and laterally extended portions ofthe gate. In another embodiments, a spacer insulator layer can havevariable thickness, with a relatively thin thickness between the fieldplate and the semiconductor layer structure and a thicker thicknessbetween the field plate and the laterally extended portions of the gate.In some embodiments, the field plate can be provided in a recess withina spacer layer in order to reduce the distance or spacing between thefield plate and the semiconductor layer structure.

While embodiments of the present invention have been described hereinwith reference to particular HEMT structures, the present inventionshould not be construed as limited to such structures, and may beapplied to formation of gate electrodes in many different transistorstructures, such as pHEMTs (including GaAs/AlGaAs pHEMTs) and/or GaNMESFETs.

Also, additional layers may be included in transistor devices whilestill benefiting from the teachings of the present invention. Suchadditional layers may include GaN cap layers, as described for exampleU.S. Pat. No. 6,548,333 to Smith. In some embodiments, insulating layerssuch as SiN_(x), or relatively high quality AlN may be deposited formaking a MISHEMT and/or passivating the surface. The additional layersmay also include a compositionally graded transition layer or layers. Inaddition, the barrier layer 22 and/or channel layer 20 described abovemay include multiple layers. Thus, embodiments of the present inventionshould not be construed as limiting these layers to a single layer butmay include, for example, barrier layers having combinations of GaN,AlGaN and/or AlN layers.

The present invention is described with reference to the accompanyingdrawings, in which embodiments of the invention are shown. However, thisinvention should not be construed as limited to the embodiments setforth herein. Rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the invention to those skilled in the art. In the drawings, thethickness of layers and regions are exaggerated for clarity. Likenumbers refer to like elements throughout.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can therefore, encompasses both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

The terminology used in the description of the invention herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the invention. As used in the description ofthe invention and the appended claims, the singular forms “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will also be understood that theterm “and/or” as used herein refers to and encompasses any and allpossible combinations of one or more of the associated listed items. Itwill be further understood that the terms “comprises” and/or“comprising,” when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe invention.

Unless otherwise defined, all terms used in disclosing embodiments ofthe invention, including technical and scientific terms, have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs, and are not necessarily limited to thespecific definitions known at the time of the present invention beingdescribed. Accordingly, these terms can include equivalent terms thatare created after such time. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe present specification and in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. All publications, patent applications,patents, and other references mentioned herein are incorporated byreference in their entirety.

In the drawings and specification, there have been disclosed typicalembodiments of the invention, and, although specific terms have beenemployed, they have been used in a generic and descriptive sense onlyand not for purposes of limitation.

That which is claimed:
 1. A transistor, comprising: a semiconductorlayer structure; a source electrode and a drain electrode on thesemiconductor layer structure; a gate on a surface of the semiconductorlayer structure between the source electrode and the drain electrode;and a field plate comprising a first portion adjacent the gate and asecond portion adjacent the source or drain electrode, wherein thesecond portion is farther from the surface of the semiconductor layerstructure than the first portion and is closer to the surface of thesemiconductor layer structure than an extended portion of the gate. 2.The transistor of claim 1, further comprising: a spacer insulator layercomprising a plurality of spacer layers that are stacked on the surfaceof the semiconductor layer to define first, second, and thirdthicknesses that separate the first portion of the field plate, thesecond portion of the field plate, and the extended portion of the gatefrom the surface of the semiconductor layer structure, respectively. 3.The transistor of claim 2, wherein the plurality of spacer layers definesubstantially coplanar surfaces at opposing sides of the gate, whereinthe extended portion of the gate laterally extends along one of thesubstantially coplanar surfaces toward the first portion of the fieldplate.
 4. The transistor of claim 3, wherein the plurality of spacerlayers comprises: a first spacer layer comprising a recess in a surfacethereof; a second spacer layer comprising a first portion in the recessand a second portion on the surface of the first spacer layer outsidethe recess, wherein the first and second portions of the second spacerlayer are between the first and second portions of the field plate andthe surface of the semiconductor layer structure, respectively; and athird spacer layer comprising the substantially coplanar surfaces on thesecond spacer layer with the field plate therebetween.
 5. The transistorof claim 3, wherein the extended portion of the gate comprises sidelobeportions that laterally extend directly along the substantially coplanarsurfaces at the opposing sides of the gate, wherein the sidelobeportions are separated from the surface of the semiconductor layerstructure by a substantially uniform distance along respective lengthsof the sidelobe portions.
 6. The transistor of claim 3, furthercomprising: sidewall spacers separating the gate from one or more of theplurality of spacer layers at the opposing sides thereof, wherein thefirst portion of the field plate laterally extends toward the gate andis separated therefrom by one of the sidewall spacers.
 7. The transistorof claim 2, wherein the field plate is a first field plate, and furthercomprising: a second field plate on a surface of the spacer insulatorlayer and extending through a portion thereof to contact the first fieldplate.
 8. The transistor of claim 2, wherein the plurality of spacerlayers comprises: a first spacer layer comprising a recess in a surfacethereof; a second spacer layer comprising a first portion in the recessand a second portion on the surface of the first spacer layer outsidethe recess, wherein the first and second portions of the second spacerlayer are between the first and second portions of the field plate andthe surface of the semiconductor layer structure, respectively; and athird spacer layer on the second spacer layer with the field platetherebetween.
 9. The transistor of claim 2, further comprising: sidewallspacers separating the gate from one or more of the plurality of spacerlayers at the opposing sides thereof, wherein the first portion of thefield plate laterally extends toward the gate and is separated therefromby one of the sidewall spacers.
 10. The transistor of claim 1, whereinthe first portion of the field plate and the extended portion of thegate laterally extend towards one another and are non-overlapping in adirection perpendicular to the surface of the semiconductor layerstructure.
 11. A transistor, comprising: a semiconductor layerstructure; a source electrode and a drain electrode on the semiconductorlayer structure; a gate on a surface of the semiconductor layerstructure between the source electrode and the drain electrode; and afield plate comprising a first portion adjacent the gate and a secondportion adjacent the source or drain electrode, wherein the secondportion is farther from the surface of the semiconductor layer structurethan the first portion, wherein the field plate is closer to the surfaceof the semiconductor layer structure than a laterally extended portionof the gate, and wherein the laterally extended portion of the gate isfree of overlap with the field plate.
 12. The transistor of claim 11,further comprising: a spacer insulator layer comprising a plurality ofspacer layers that are stacked on the surface of the semiconductor layerto define first, second, and third thicknesses that separate the firstportion of the field plate, the second portion of the field plate, andthe laterally extended portion of the gate from the surface of thesemiconductor layer structure, respectively.
 13. The transistor of claim12, wherein the plurality of spacer layers define substantially coplanarsurfaces at opposing sides of the gate, and wherein the laterallyextended portion of the gate comprises sidelobe portions that laterallyextend directly along the substantially coplanar surfaces at theopposing sides of the gate.
 14. The transistor of claim 13, wherein theplurality of spacer layers comprises: a first spacer layer comprising arecess in a surface thereof; a second spacer layer comprising a firstportion in the recess and a second portion on the surface of the firstspacer layer outside the recess, wherein the first and second portionsof the second spacer layer are between the first and second portions ofthe field plate and the surface of the semiconductor layer structure,respectively; and a third spacer layer comprising the substantiallycoplanar surfaces on the second spacer layer with the field platetherebetween.
 15. The transistor of claim 12, wherein the field plate isa first field plate, and further comprising: a second field plate on asurface of the spacer insulator layer and extending through a portionthereof to contact the first field plate.
 16. The transistor of claim12, wherein the plurality of spacer layers comprises: a first spacerlayer comprising a recess in a surface thereof; a second spacer layercomprising a first portion in the recess and a second portion on thesurface of the first spacer layer outside the recess, wherein the firstand second portions of the second spacer layer are between the first andsecond portions of the field plate and the surface of the semiconductorlayer structure, respectively; and a third spacer layer on the secondspacer layer with the field plate therebetween.
 17. A transistor,comprising: a channel layer and a barrier layer defining aheterojunction therebetween; a source electrode and a drain electrode onthe barrier layer; a gate on the barrier layer and comprising sidelobeportions laterally extending from opposing sides of the gate toward thesource electrode and the drain electrode, respectively; a field plate onthe barrier layer between the gate and the drain electrode; and a spacerinsulator layer comprising a plurality of spacer layers with the fieldplate therebetween, wherein the spacer layers are stacked on the barrierlayer at the opposing sides of the gate and separate the sidelobeportions of the gate from the barrier layer by a substantially uniformdistance along respective lengths of the sidelobe portions.
 18. Thetransistor of claim 17, wherein the plurality of spacer layers definesubstantially coplanar surfaces at the opposing sides of the gate withthe sidelobe portions of the gate laterally extending directly thereon.19. The transistor of claim 18, wherein the spacer layers have asubstantially uniform thickness at the opposing sides of the gate. 20.The transistor of claim 18, wherein the field plate comprises a firstportion adjacent the gate and a second portion adjacent the drainelectrode, wherein the second portion is farther from a surface of thebarrier layer than the first portion.
 21. The transistor of claim 20,wherein the first portion of the field plate and one of the sidelobeportions of the gate laterally extend towards one another and arenon-overlapping in a direction perpendicular to the surface of thebarrier layer.
 22. The transistor of claim 17, wherein the field plateis a first field plate, and further comprising: a second field plate ona surface of the spacer insulator layer and extending through a portionthereof to contact the first field plate.
 23. A transistor, comprising:a channel layer and a barrier layer defining a heterojunctiontherebetween; a source electrode and a drain electrode on the barrierlayer; a gate on the barrier layer and comprising sidelobe portionslaterally extending from opposing sides of the gate toward the sourceelectrode and the drain electrode, respectively; a field plate on thebarrier layer between the gate and the drain electrode, wherein thefield plate comprises a first portion adjacent the gate and a secondportion adjacent the drain electrode, wherein the second portion isfarther from a surface of the barrier layer than the first portion; aspacer insulator layer comprising a plurality of spacer layers with thefield plate therebetween, wherein the spacer layers are stacked on thebarrier layer at the opposing sides of the gate and separate thesidelobe portions of the gate from the barrier layer; and sidewallspacers separating the gate from the plurality of spacer layers at theopposing sides thereof, wherein the first portion of the field platelaterally extends toward the gate and is separated therefrom by one ofthe sidewall spacers.
 24. A method of fabricating a transistor, themethod comprising: forming a channel layer and a barrier layer defininga heterojunction therebetween; forming a source electrode, a drainelectrode, and a gate on the barrier layer, wherein the gate comprisessidelobe portions laterally extending from opposing sides of the gatetoward the source electrode and the drain electrode, respectively; andforming a spacer insulator layer and a field plate on the barrier layer,the spacer insulator layer comprising a plurality of spacer layers withthe field plate therebetween, wherein the spacer layers are stacked onthe barrier layer at the opposing sides of the gate and separate thesidelobe portions of the gate from the barrier layer by a substantiallyuniform distance along respective lengths of the sidelobe portions. 25.The method of claim 24, wherein the plurality of spacer layers definesubstantially coplanar surfaces with the sidelobe portions of the gatelaterally extending directly thereon.
 26. The method of claim 24,wherein the field plate comprises a first portion adjacent the gate anda second portion adjacent the source or drain electrode, wherein thesecond portion is farther from a surface of the barrier layer than thefirst portion.
 27. The method of claim 24, wherein the field plate is afirst field plate, and further comprising: forming an opening extendingthrough the spacer insulator layer to expose the first field plate; andforming a second field plate on a surface of the spacer insulator layerand extending into the opening to contact the first field plate.
 28. Amethod of fabricating a transistor, the method comprising: forming achannel layer and a barrier layer defining a heterojunctiontherebetween; forming a source electrode, a drain electrode, and a gateon the barrier layer, wherein the gate comprises sidelobe portionslaterally extending from opposing sides of the gate toward the sourceelectrode and the drain electrode, respectively; and forming a spacerinsulator layer and a field plate on the barrier layer, the spacerinsulator layer comprising a plurality of spacer layers with the fieldplate therebetween, wherein the spacer layers are stacked on the barrierlayer at the opposing sides of the gate and separate the sidelobeportions of the gate from the barrier layer, wherein the field platecomprises a first portion adjacent the gate and a second portionadjacent the source or drain electrode, wherein the second portion isfarther from a surface of the barrier layer than the first portion, andwherein forming the spacer insulator layer and the field platecomprises: forming a first spacer layer comprising a recess in a surfacethereof; forming a second spacer layer comprising a first portion in therecess and a second portion on the surface of the first spacer layeroutside the recess; forming the first and second portions of the fieldplate on the first and second portions of the second spacer layer,respectively; and forming a third spacer layer on the second spacerlayer and the first and second portions of the field plate.
 29. Themethod of claim 28, wherein the field plate is a first field plate, andfurther comprising: forming an opening extending through the thirdspacer layer to expose at least one of the first or second portions ofthe first field plate; and forming a second field plate on the thirdspacer layer and extending into the opening to contact the first fieldplate.